Astera Labs PT4080L PCI Express® Gen-4 x8 Smart Retimer
Astera Labs PT4080L PCI Express® Gen-4 x8 Smart Retimer is designed to integrate a Root Complex and End Point(s) extending the reach by >28dB at 16 GT/s. The PT4080L is compliant to all PCIe 4.0 rates and Retimer functional requirements. The device enables more system topologies and lowers total solution cost while minimizing implementation overhead and Bill of Materials (BoM).
Features
- Compatible with PCIe Gen-4/3/2/1
- 16 GT/s, 8 GT/s, 5 GT/s, and 2.5 GT/s Data Rates with Automatic Link Equalization
- Low-Latency Mode Enables Cache-Coherent Links
- Eight Lanes with Flexible Link Bifurcation Including 1x8, 2x4, 4x2, and Others
- Extends Reach by >28 dB at 16 GT/s Enabling LowCost PCB Materials and Connectors
- Receiver and Transmitter Performance Exceeds PCI Express® Base Specification Requirements
- No System Software Required
- BGA Package Footprint Optimized for Board Routing
- Supports SRIS, SRNS, and Common Clock Systems
- Supports Hot Plug and Hot Un-Plug
- Supports Lane Margining at the Receiver for Both Timing and Voltage
- Supports Slave Loopback
- Supports Systems with Lane Reversal and Implements Automatic Polarity Correction
- Low-Power Advanced CMOS Process
- HCSL Reference Clock Output Eliminates Clock Buffers to Drive Downstream PCIe Components
- Advanced In-Band and Out-of-Band Diagnostics for Fleet Management, Large-Scale Server Deployments
- Full-Featured C and Python SDKs for Rapid Integration of Advanced Diagnostics Features
- Device Configuration through SMBus or EEPROM
- IEEE 1149.6 AC-JTAG Boundary Scan
- Full Portfolio of Pin- and Register-Compatible Retimers Enables Easy Performance Scaling Up to PCI Express® Gen-5
Applications
- Server and high-performance PC motherboards
- PCIe riser and add-in cards
- Server-to-server cabled interfaces
- NVMe JBOFs, GPU/deep-learning accelerators
Typical Application Block Diagram
Zveřejněno: 2021-01-28
| Aktualizováno: 2022-03-11